1. Field of the Invention
This present invention relates to a phase detector, clock distribution circuit, and Large Scale Integration to adjust a clock skew.
2. Description of the Related Art
It is important to reduce a clock skew in a synchronous circuit because a large clock skew causes a set-up time/hold time violation. Accordingly, a Large Scale Integration (LSI) operating at high frequency especially at gigahertz clock speed is designed to reduce the skew as required. Therefore, a balanced tree of clock buffers shown in FIG. 1 is used. The balanced tree is technique to distribute the clock with reduced skew to a large number of flip-flops (F/Fs) in the LSI. The F/Fs layed out in a plurality of domains in the LSI are clustered, and the F/Fs in the same cluster are connected to the domain clock buffer with the same propagation delay. For example, as shown in FIG. 1, the F/Fs are connected to each of domain clock buffers 1a to 1h. Then, the domain clock buffers are clustered and connected to another buffer with the same propagation delay. For example, the cluster of domain clock buffers 1a, 1b, 1e, 1f in domains A, B, E, F is connected to a buffer 2a and the cluster of domain clock buffers 1c, 1d, 1g, 1h in domains C, D, G, H is connected to a buffer 2d. Buffers are connected to a clock source with the same propagation delay. In such a way, the balanced tree is designed from bottom-up.
However, even for a balanced tree so designed, the skew still remains in the manufactured LSI because of difficulty of wiring all of the buffers with the same propagation delay or wire capacitance. Therefore, there is a method whereby a phase detector (PD) located in the boundary of the domain detects the skew between two domain clock buffers in two domains that face across the tile boundary and reduces the skew in the manufactured LSI by adjusting the propagation delay of the buffers.
However, as shown in FIG. 2, the phase detectors PD1 to PD24 placed at the boundary of domain A to P in the LSI 5 detect the skew between only two domain clock buffers. For example, the phase detector PD 3 detects the skew between clock CK-B transmitted from the domain clock buffer 1b in the domain B and clock CK-F transmitted from the domain clock buffer 1f in the domain F. Because phase detectors are mounted at the every boundary of the two domains facing across each of the boundaries, the number of phase detectors is large and a large number of the phase detectors creates difficulties in the layout and wire planning of the LSI and increases the LSI area.
In particular, an LSI operating at high clock speed above 1 gigahertz requires minimal skew. The more the LSI area is broken into domains for minimizing the skew, the larger the number of phase detectors. The larger the integration of the LSI, and the larger the number of domains of the LSI and phase detectors.